View AD8116_2166956.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD8116 * one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 functional block diagram AD8116 switch matrix output buffer enable/disable 80 80 256 parallel latch decode 16 5:16 decoders 16 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 clk data in update ce reset 16 inputs clk data out update ce reset 16 outputs set individual or reset all outputs to "off" 80-bit shift reg. 200 mhz, 16 16 buffered video crosspoint switch frequency ?hz 4 3 ? 100k 1g 1m magnitude ?db 10m 100m 0 ? ? ? 2 1 0.5 0.4 ?.3 0 ?.1 ?.2 0.3 0.2 0.1db flatness ?db 0.1 2v p-p 200mv p-p flatness r l = 50 200mv p-p 2v p-p figure 1. frequency response features large 16 16 high speed nonblocking switch array switch array controllable via an 80-bit serial word serial data out allows daisy chaining of multiple AD8116s to create large switch arrays over 256 256 complete solution buffered inputs 16 individual output amplifiers drives 150 loads excellent video performance 60 mhz 0.1 db gain flatness 0.01% differential gain error (r l = 150 ) 0.01 differential phase error (r l = 150 ) excellent ac performance 200 mhz C3 db bandwidth 300 v/ s slew rate low power of 900 mw (3.5 mw per point) low all hostile crosstalk of C70 db @ 5 mhz output disable allows direct connection of multiple device outputs chip enable allows selection of individual AD8116s in large arrays (or parallel programming of AD8116s) reset pin allows disabling of all outputs (connected through a capacitor to ground provides power- on reset capability) 128-lead lqfp package (14 mm 14 mm) applications routing of high speed signals including: composite video (ntsc, pal, s, secam, etc.) component video (yuv, rgb, etc.) 3-level digital (hdb3) video on demand ultrasound communication satellites product description the AD8116 is a high speed 16 16 video crosspoint switch matrix. it offers a 3 db signal bandwidth greater than 200 mhz and channel switch times of 60 ns with 0.1% settling. with ?0 db of crosstalk and ?05 db of isolation (@ 5 mhz), the AD8116 is useful in many high speed applications. the differential gain and differential phase errors of better than 0.01% and 0.01 , respectively, along with 0.1 db flatness out to 60 mhz make the AD8116 ideal for video signal switching. the AD8116 includes output buffers that can be placed into a high impedance state for paralleling crosspoint outputs so that off channels do not load the output bus. it operates on voltage supplies of 5 v while consuming only 90 ma of idle current. the channel switching is performed via a serial digital control that can accommodate ?aisy chaining?of several devices. the AD8116 is packaged in a 128-lead lqfp package occupy- ing only 0.36 square inches, and is specified over the commer- cial temperature range of 0 c to 70 c. * patent pending.
C2C rev. b AD8116?pecifications (v s = 5 v, t a = 25 c, r l = 1 k unless otherwise noted.) limit reference parameter conditions min typ max unit figure dynamic performance ? db bandwidth 200 mv p-p, r l = 150 ? 200 mhz 1 1 v p-p, r l = 150 ? 120 mhz 2 v p-p, r l = 150 ? 80 mhz 1 slew rate 2 v step, r l = 150 ? 300 v/ s5 settling time 0.1%, 2 v step, r l = 150 ? 60 ns 6 gain flatness 0.05 db, 200 mv p-p, r l = 150 ? 25 mhz 1 0.05 db, 2 v p-p, r l = 150 ? 20 mhz 1 0.1 db, 200 mv p-p, r l = 150 ? 60 mhz 1 0.1 db, 2 v p-p, r l = 150 ? 45 mhz 1 noise/distortion performance differential gain error ntsc or pal, r l = 1 k ? 0.01 % ntsc or pal, r l = 150 ? 0.01 % differential phase error ntsc or pal, r l = 1 k ? 0.01 degrees ntsc or pal, r l = 150 ? 0.01 degrees crosstalk, all hostile ?= 5 mhz ?0 db 2 ?= 10 mhz ?0 db 2 off isolation, input-output = 10 mhz, r l = 150 ? , one channel ?05 db 11 input voltage noise 0.01 mhz to 50 mhz 15 nv/ hz 8 dc performance gain no load 0.995 0.999 1.000 v/v r l = 1 k ? 0.992 0.999 1.000 v/v gain matching no load, ch-ch 0.15 % r l = 1 k ? , ch-ch 0.5 % output characteristics output offset voltage worst-case all switch configurations 15 45 mv 17 output impedance dc, enabled 0.2 ? 12 disabled 1 10 m ? 9 output disable capacitance 3 pf 9 output leakage current disabled 1 a output voltage range 2.5 3v output current 20 40 ma short circuit current 65 ma input characteristics input voltage range 2.5 3v input capacitance any switch configuration 5 pf 13 input resistance 1 10 m ? 13 input bias current 25 a switching characteristics enable on time 60 ns switching time 50% update to 1% output settling, 50 ns 16 2 v step switching transient (glitch) 15 mv p-p 10 power supplies supply current avcc, outputs enabled, no load 75 95 ma avcc, outputs disabled 25 ma avee, outputs enabled, no load 70 95 ma avee, outputs disabled 22.5 ma dvcc, outputs enabled, no load 25 35 ma dvee, outputs enabled, no load 10 15 ma supply voltage range 4.5 to 5.5 v psrr ?= 100 khz 60 db 7 ?= 1 mhz 40 db 7 operating temperature range temperature range operating (still air) 0 to 70 c ja operating (still air) 37 c/w specifications subject to change without notice.
AD8116 C3C rev. b timing characteristics limit parameter symbol min typ max unit data setup time t 1 20 ns clk pulsewidth t 2 100 ns data hold time t 3 20 ns clk pulse separation t 4 100 ns clk to update delay t 5 0ns update pulsewidth t 6 50 ns clk to data out valid t 7 200 ns propagation delay, update to switch on or off 50 ns data load time, clk = 5 mhz 16 s clk, update rise and fall times 100 ns reset time 200 ns load data into serial register on falling edge 1 0 1 0 data in clk 1 = latched update 0 = transparent data out out15 (d4) out15 (d3) out00 (d0) transfer data from serial register to parallel latches during low level t 1 t 3 t 7 t 2 t 4 t 6 t 5 clock data in update 12 34 5 67 8 910 15 20 25 75 79 t = 0 increasing time enable output 15 enable output 14 connect to input 01 disable output 13 don t care enable output 12 connect to input 15 connect to input 03 connect to nput 00 enable output 11 enable output 00 connect to input 00 0 figure 2. timing diagram and programming example table i. logic levels v ih v il v oh v ol i ih i il i oh i ol clk, data in, clk, data in, data out data out clk, data in, clk, data in, data out data out ce , update ce , update ce , update ce , update 2.0 v min 0.8 v max 2.7 v min 0.5 v max 20 a max ?00 a min ?00 a max 3.0 ma min
AD8116 C4C rev. b caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD8116 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. maximum power dissipation the maximum power that can be safely dissipated by the AD8116 is limited by the associated rise in junction tempera- ture. the maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150 c. temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of 175 c for an extended period can result in device failure. while the AD8116 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temp- erature (150 c) is not exceeded under all conditions. to ensure proper operation, it is necessary to observe the maximum power derating curves shown in figure 3. ambient temperature c 5.0 maximum power dissipation watts 4.0 0 50 80 40 30 20 10 0 10203040506070 3.0 2.0 1.0 t j = 150 c 90 figure 3. maximum power dissipation vs. temperature absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.0 v internal power dissipation 2 AD8116 128-lead plastic lqfp (st) . . . . . . . . . . . . 3.5 w input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s output short circuit duration . . . . . . . . . . . . . . . . . . . . observe power derating curves storage temperature range . . . . . . . . . . . . 65 c to +125 c lead temperature range (soldering 10 sec) . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device in free air (t a = 25 c): 128-lead plastic lqfp (st): ja = 37 c/w. ordering guide temperature package package model range description option AD8116jst 0 c to 70 c 128-lead plastic lqfp st-128a (14 mm 14 mm) AD8116-eb evaluation board warning! esd sensitive device
AD8116 C5C rev. b table ii. operation truth table control lines ce update clk data in data out reset operation/comment 1 x x x x 1 no change in logic. 01 f data i data i-80 1 the data on the data in line is loaded into the serial register. the first bit clocked into the serial register appears at data out 80 clocks later. 0 0 x x x 1 data in the serial shift register transfers into the parallel latches that control the switch array. latches are transparent. x x x x x 0 asynchronous operation. all outputs are disabled. remainder of logic is unchanged. 256 decode switch matrix le d le d le d le d le d le d le d le d le d le d le d le d en 0 lsb 123en msb 0 lsb 12 3en msb 0 clrqqqqqq clr clr q q qq qq 54 321 0 79 78 77 76 75 74 out14 out15 out15 out15 out15 out15 out0 out0 out0 out0 out0 out1 dddddd qqqqqq clk clk clk clk clk clk dddddd qqqqqq clk clk clk clk clk clk output ch ch bit # serial bit # data in data out reset update ce clk output enable 16 figure 4. logic diagram
AD8116 C6C rev. b pin function descriptions pin name pin numbers pin description inxx 2, 4, 6, 8, 10, 12, 14, 16, 18, a nalog inputs; xx = channel no. 00 thru 15. 20, 22, 24, 26, 28, 30, 32 data in 37, 126 serial data input, ttl compatible. clk 36, 125 serial clock, ttl compatible. falling edge triggered. data out 35, 124 serial data out, ttl compatible. update 38, 123 enable (transparent) ?ow.?allows serial register to connect directly to switch matrix. data latched when ?igh. reset 39, 122 disable outputs, enable ?ow. ce 40, 121 chip enable, enable ?ow.? must be ?ow?to clock in & latch data. outyy 65, 67, 69, 71, 73, 75, 77, 79, a nalog outputs yy = channel nos. 00 thru 15. 81, 83, 85, 87, 89, 91, 93, 95 agnd 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, a nalog ground for inputs and switch matrix. 21, 23, 25, 27, 29, 31, 33, 128 dvcc 34, 127 +5 v for digital circuitry. dgnd 41, 120 ground for digital circuitry. dvee 42, 119 ? v for digital circuitry. avee 43, 44, 45, 116, 117, 118 5 v for inputs and switch matrix. avcc 46, 47, 48, 113, 114, 115 +5 v for inputs and switch matrix. agndxx 56?3, 97?04 ground for output amp, xx = output channel nos. 00 thru 15. must be connected. avcc00 96 +5 v for output channel 00. must be connected. avcc15 64 +5 v for output channel 15. must be connected. avccxx/yy 68, 72, 76, 80, 84, 88, 92 +5 v for output amplifier that is shared by channel nos. xx and yy. must be connected. aveexx/yy 66, 70, 74, 78, 82, 86, 90, 94 5 v for output amplifier that is shared by channel nos. xx and yy. must be connected. figure 5. i/o pin schematics esd esd input v cc v ee a. analog input esd esd output v cc v ee b. analog output esd esd reset v cc 20k c. reset input esd esd input v cc v ee d. logic input esd esd output v cc v ee 2k e. logic output
AD8116 C7C rev. b pin configuration 34 35 36 37 38 40 41 42 43 44 45 46 47 48 49 50 51 52 33 39 64 63 62 61 60 59 56 55 54 53 58 57 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 26 25 28 27 30 29 32 31 5 4 3 2 7 6 9 8 1 120 121 122 123 124 125 126 127 12 8 119 111 118 117 116 115 114 113 112 110 109 108 10 7 10 6 10 5 10 4 10 3 10 2 101 10 0 99 98 97 92 93 95 90 91 88 89 87 96 86 94 81 82 83 84 79 80 78 76 77 85 75 73 74 71 72 69 70 67 68 66 65 pin 1 identifier top view (not to scale) agnd dvcc data in clk data out update reset ce dgnd dvee avee avee avee avcc avcc avcc nc nc nc nc agnd dvcc data out clk data in update reset ce dgnd dvee avee avee avee avcc avcc avcc nc nc nc nc avcc00 out00 avee00/01 out01 avcc01/02 out02 avee02/03 out03 avcc03/04 out04 avee04/05 out05 avcc05/06 avee10/11 out11 avcc11/12 out12 avee12/13 out13 avcc13/14 out14 agnd in00 agnd in01 agnd in02 agnd in03 agnd in04 agnd in05 agnd in06 agnd in07 agnd in08 agnd in09 agnd in10 agnd in11 agnd in12 agnd in13 agnd in14 agnd in15 nc nc nc agnd15 agnd14 agnd13 agnd12 agnd11 agnd10 agnd09 agnd08 avcc15 avee14/15 out15 nc nc nc nc agnd00 agnd01 agnd02 agnd03 agnd04 agnd05 agnd06 agnd07 out06 avee06/07 out07 avcc07/08 out08 avee08/09 out09 avcc09/10 out10 AD8116 128l lqfp (14mm x 14mm) nc = no connect
AD8116 C8C rev. b 100mv p-p 100ns/div 25mv/div tpc 4. step response, 100 mv step 100ns/div 500mv/div 2v p-p tpc 5. step response, 2 v step 2mv/div = 0.1%/div 20ns/div 0 20 40 60 80 100 120 140 160 180 2v step r l = 150 tpc 6. settling time typical performance characteristics frequency hz 4 3 4 100k 1g 1m magnitude db 10m 100m 0 1 2 3 2 1 0.5 0.4 0.3 0 0.1 0.2 0.3 0.2 flatness db 0.1 2v p-p 200mv p-p flatness r l = 150 c l = 0pf 200mv p-p 2v p-p tpc 1. frequency response frequency hz 10 20 100 300k 200m 1m 10m 100m crosstalk db 50 70 80 90 30 40 60 r l = 1k r s = 37.5 all hostile crosstalk v in = 632mv p-p adjacent channel crosstalk v in = 632mv p-p tpc 2. crosstalk vs. frequency harmonic distortion db 0 10 100 20 30 40 50 60 70 80 90 frequency hz 100k 1m 10m 100m 2nd harmonic v in = 2v p-p, r l = 150 3rd harmonic tpc 3. total harmonic distortion
5 4 3 2 1 0 20 10 0 10 20 1v/div 10mv/div 50ns/div tpc 10. switching transient (glitch) frequency hz 50 60 150 100k 500m 1m 10m 100m 90 120 130 140 70 80 110 100 off isolation db v in = 2v p-p tpc 11. off isolation, input-output output impedance frequency hz 10,000 0.1 100k 500m 1m 10m 100m 100 1 1000 10 tpc 12. output impedance, enabled frequency hz power supply rejection db 20 30 70 10k 10m 100k 1m 40 50 60 tpc 7. psrr vs. frequency frequency hz 316 100 3.16 10 100m 100 nv/ hz 1k 10k 100k 1m 10m 31.6 10 tpc 8. voltage noise vs. frequency frequency hz 10m 100 100k 500m 1m 10m 100m 100k 1k 1m 10k output impedance tpc 9. output impedance, disabled typical performance characteristics AD8116 C9C rev. b
AD8116 C10C rev. b input impedance frequency hz 10m 100 100k 500m 1m 10m 100m 100k 1k 1m 10k 30k tpc 13. input impedance vs. frequency 15 100k 500m 1m 10m 100m 12 30pf v in = 200mv r l = 150 30k 9 6 3 0 3 6 9 12 15 frequency hz gain db 18pf 12pf tpc 14. frequency response vs. capacitive load flatness db frequency hz 0.5 100k 1m 10m 100m 30k 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 c l = 18pf c l = 12pf c l = 30pf v in = 200mv r l = 150 tpc 15. flatness vs. capacitive load vout 100mv, 50ns u pdate tpc 16. switching time 0.035 0.025 0.025 0.015 0.005 0.005 0.015 170 160 frequency 140 100 150 130 120 110 90 70 30 80 60 50 40 0 20 10 offset voltage volts tpc 17. offset voltage distribution temperature c 2.0 2.0 60 100 40 20 0 20 40 60 80 1.5 0.0 0.5 1.0 1.5 1.0 0.5 v os mv tpc 18. offset voltage drift vs. temperature
AD8116 C11C rev. b theory of operation loading data data to control the switches is clocked serially into an 80-bit shift register and then transferred in parallel to an 80-bit latch. the falling edge of clk (the serial clock input) loads data into the shift register. the first five bits of the 80 bits are loaded via data in (the serial data input) program out15. the first of the five bits (d4) enables or disables the output. the next four bits (d3?0, d3 = msb, d0 = lsb) determine which one of the 16 inputs will be connected to out15 (only one of the 16 inputs can be connected to a given output). the remaining bits program out14 through out00. after the shift register is filled with the new 80 bits of control data, update is activated (low) to transfer the data to the parallel latches. the switch control latches are static and will hold their data as long as power is applied. to extend the number of switches in an array, the data out and data in pins of m ultiple AD8116s can be daisy- chained together. the data out pin is the end of the shift register and may be directly connected to the data in pin of the follow-on AD8116. ce can be used to control the clocking of data into selected devices. serial logic the AD8116 employs a serial interface for programming the state of the crosspoint array. the 80-bit shift register (figure 4) consists of static d flip-flops while the parallel latch uses transparent latches that are latched by a logic high state of update , and transparent on logic low of the same signal. the 4-to-16 decoder is a small current-mode multilevel gate array that steers a small select current to the selected point in the crosspoint array. the reset signal is connected to only the enable/disable bit on each output buffer. this means that the AD8116 will have a ran- dom configuration on power-up. in normal operation though, reset and update can be used together to alternately enable and disable an entire array at once, if desired. separate chip enable ( ce ), update ( update ) and serial data out (data out) signals allow several options for program- ming larger arrays of AD8116s. the function of each bit in the 80-bit word that programs the state of the AD8116 is shown in figure 4. in normal operation, the data out pin of one AD8116 is conn ected to the data in of the next. in this way, for example, an ar ray of eight AD8116s would be programmed with one 640-bit sequence. in this mode ce is logic low and the clk and update pins are connected in parallel. in one alternate mode of programming, the ce pin can be used to select one AD8116 at a time. this might be desirable when the ability to program just one device at a time is required. in this mode clk, update and data in are all connected in parallel. the user then selects each AD8116 in turn (with the ce signal) and programs it with the desired data. larger arrays can also be programmed by connecting each data in signal to a larger parallel bus. in this way only 80 clock cycles would be needed to program the entire array. the logic signals are con- figured so that all programming can be accomplished with synchronous logic and a continuous clock, so that no missing cycles or delays need be generated. applications multichannel video the excellent video specifications of the AD8116 make it an ideal candidate for creating composite video crosspoint switches. these can be made quite dense by taking advantage of the AD8116? high level of integration and the fact that composite video requires only one crosspoint channel per system video channel. there are, however, other video formats that can be routed with the AD8116 requiring more than one crosspoint channel per video channel. some systems use twisted pair wiring to carry video signals. these systems utilize differential signals and can lower costs because they use lower cost cables, connectors and termination methods. they also have the ability to lower crosstalk and reject common-mode signals, which can be important for equip- ment that operates in noisy environments or where common- mode voltages are present between transmitting and receiving equipment. in such systems, the video signals are differential; there is a positive and negative (or inverted) version of the signals. these complementary signals are transmitted onto each of the two wires of the twisted pair, yielding a first order zero common- mode voltage. at the receive end, the signals are differentially received and converted back into a single-ended signal. when switching these differential signals, two channels are required in the switching element to handle the two differential signals that make up the video channel. thus, one differential video channel is assigned to a pair of crosspoint channels, both input and output. for a single AD8116, eight differential video channels can be assigned to the 16 inputs and 16 outputs. this will effectively form an 8 8 differential crosspoint switch. programming such a device will require that inputs and outputs be programmed in pairs. this information can be deduced by inspection of the programming format of the AD8116 and the requirements of the system. there are other analog video formats requiring more than one analog circuit per video channel. one two-circuit format that is more commonly being used in systems such as satellite tv, digital cable boxes and higher quality vcrs, is called s-video or y/c video. this format carries the brightness (luminance or y) portion of the video signal on one channel and the color (chromi- nance or c) on a second channel. since s-video also uses two separate circuits for one video chan- nel, creating a crosspoint system requires assigning one video channel to two crosspoint channels as in the case of a differen- tial video system. aside from the nature of the video format, other aspects of these two systems will be the same. there are yet other video formats using three channels to carry the video information. video cameras produce rgb (red, green, blue) directly from the image sensors. rgb is also the usual format used by computers internally for graphics. rgb can also be converted to y, r-y, b-y format, sometimes called yuv format. these three-circuit video standards are referred to as component analog video. the three-circuit video standards require three crosspoint chan- nels per video channel to handle the switching function. in a fashion similar to the two-circuit video formats, the inputs and outputs are assigned in groups of three and the appropriate logic programming is performed to route the video signals.
AD8116 C12C rev. b using additional crosspoint devices in the design can lower the number of outputs that have to be wire-ored together. figure 26 shows a block diagram of a system using ten AD8116s to create a nonblocking 128 16 crosspoint that restricts the wire- oring at the output to only four outputs. this will prevent an enabled output from having to drive a large number of disabled devices. additionally, by using the lower eight outputs from each of the two rank 2 AD8116s, a blocking 128 32 crosspoint array can be realized. there are, however, some drawbacks to this technique. the offset voltages of the various cascaded devices will accumulate and the bandwidth limitations of the devices will compound. in addition, the extra devices will consume more current and take up more board space. once again, the overall system design specifications will determine how to make the various trade-offs. in out AD8116 in out AD8116 16 0 15 in AD8116 in out AD8116 16 16 31 16 16 out 16 31 0 15 16 31 in in out 0 15 out figure 6. 32 32 crosspoint array using four AD8116s in out AD8116 in out AD8116 in AD8116 16 0 15 in out AD8116 in AD8116 in AD8116 16 16 31 in AD8116 in AD8116 in AD8116 16 32 47 16 16 16 out 0 15 out 16 31 out 32 47 in in in out out out out out out figure 7. 48 48 crosspoint array using nine AD8116s creating larger crosspoint arrays the AD8116 is a high density building block for crosspoint arrays over 256 256. various features such as output disable, chip enable, serial data out and multiple pinouts for logic signals are very useful for the creation of these larger arrays. the first consideration in constructing a larger crosspoint is to determine the minimum number of devices that are required. the 16 16 architecture of the AD8116 contains 256 ?oints, which is a factor of four greater than an 8 8 crosspoint and a factor of 64 greater than a 4 1 crosspoint. the pc board area and power consumption savings are readily apparent when compared to using these smaller devices. for a nonblocking crosspoint, the number of points required is the product of the number of inputs multiplied by the number of outputs. nonblocking requires that the programming of a given input to one or more outputs does not restrict the avail- ability of that input to be a source for any other outputs. thus a 32 32 crosspoint will require 1024 points. this number is then divided by 256, or the number of points in one AD8116 device, to yield four in this case. this says that the minimum number of 16 16 devices required for a fully programmable 32 32 crosspoint is four. some nonblocking crosspoint architectures will require more than this minimum as calculated above. also, there are blocking architect ures that can be constructed with fewer devices than this minimum. th ese systems have connectivity available on a statis- tical basis that is determined when designing the overall system. the basic concept in constructing larger crosspoint arrays is to connect inputs in parallel in a horizontal direction and to ?ire- or?the outputs together in the vertical direction. the meaning of horizontal and vertical can best be understood by looking at a diagram. fi gure 6 illustrates this concept for a 32 32 crosspoint array. a 48 48 crosspoint is illustrated in figure 7. the 32 32 crosspoint requires each input driver drive two inputs in parallel and each output be wire-ored with one other output. the 48 48 crosspoint requires driving three inputs in parallel and having the outputs wire-ored in groups of three. it is required of the system programming that only one output of a wired-or node be active at a time. it is not essential that crosspoint architectures be square. for example, a 64 16 crosspoint array can be constructed with four AD8116s by driving each input with a separate signal and wire-oring together the corresponding outputs of each device. it can be seen, however, that by going to larger arrays the number of disabled outputs an active output has to drive starts to increase. at some point, the number of outputs that are wire-ored becomes too great to maintain system performance. this will vary according to which system specifications are most important. for example, a 128 16 crosspoint can be created with eight AD8116s. this design will have 128 separate inputs and have the corresponding outputs of each device wire-ored together in groups of eight.
AD8116 C13C rev. b 8 8 16 16 in 16 31 16 in 0 15 16 16 16 16 16 out 0 16 in 32 47 in 48 63 in 64 79 in 80 95 in 96 111 in 112 127 nonblocking outputs additional 16 outputs rank 2 32:16 nonblocking (32:32 blocking) 8 8 8 8 8 rank 1 (128:32) four AD8116 outputs wire-ored together 8 8 8 8 8 8 8 8 8 8 8 8 8 figure 8. nonblocking 128 16 array (128 32 blocking) logic operation there are two basic options for controlling the logic in multi- crosspoint arrays. one is to serially connect the data paths (data out to data in) of all the devices and tie all the clk and update signals in parallel. ce can be tied low for all the devices. a long serial sequence with the desired programming data consisting of 80 bits times the number of AD8116 devices can then be shifted through all the parallel devices by using the data in of the first device and the clk. when finished clocking in the data, update can be pulled low to program all the device crosspoint matrices. this technique has an advantage in that a separate ce signal is not required for each chip, but has a disadvantage in that several chips data cannot be shifted in parallel. in addition, if another device is added into the system between already existing devices, the pro- gramming sequence will have to be lengthened at some midpoint to allow for programming of the added device. the second programming method is to connect all the clk and the data in pins in parallel and use the ce pins in sequence to program each device. if a byte or 16-bit word of data is available for providing the programming data, then multiple AD8116s can be programmed in parallel with just 80 clock cycles. this method can be used to speed up the programming of large arrays. of course, in a practical system, various combinations of these basic methods can be used. power-on reset most systems will want all the AD8116s to be in the reset state (all outputs disabled) when power is applied to the system. this ensures that two outputs that are wire-ored together will not fight each other at power up. the power-on reset function can be implemented by adding a 0.1 f capacitor from the reset pin to ground. this will hold this signal low after the power is applied to reset the device. an on-chip 20 k ? resistor from reset to dvcc will charge the capacitor to the logical high state. if several AD8116s are used, the pull-up resistors will be in parallel, so a larger value capaci- tance should be used. if the system requires the ability to be reset while power is still applied, the reset driver will have to be able to charge and discharge this capacitance in the required time. with too many devices in parallel, this might become more difficult; if this occurs, the reset circuits should be broken up into smaller sub- sets with each controlled by a separate driver. crosstalk many systems, such as broadcast video, that handle numerous analog signal channels have strict requirements for keeping the various signals from influencing any of the others in the system. crosstalk is the term used to describe the coupling of the signals of other nearby channels to a given channel. when there are many signals in close proximity in a system, as will undoubtedly be the case in a system that uses the AD8116, the crosstalk issues can be quite complex. a good understanding of the nature of crosstalk and some definition of terms is requ ired in order to specify a system that uses one or more AD8116s. types of crosstalk crosstalk can be propagated by means of any of three meth ods. these fall into the categories of electric field, magnetic field and sharing of common impedances. this section will explain these effects. every conductor can be both a radiator of electric fields and a receiver of electric fields. the electric field crosstalk mecha- nism occurs when the electric field created by the transmitter propagates across a stray capacitance and couples with the receiver and induces a voltage. this voltage is an unwanted crosstalk signal in any channel that receives it. currents flowing in conductors create magnetic fields that circulate around the currents. these magnetic fields will then generate voltages in any other conductors whose paths they link. the undesired induced voltages in these other channels are crosstalk signals. the channels that crosstalk can be said to have a mutual inductance that couples signals from one channel to another. the power supplies, grounds and other signal return paths of a multichannel system are generally shared by the various chann els. when a current from one channel flows in one of these paths, a voltage that is developed across the impedance becomes an input crosstalk signal for other channels that share the common impedance. all these sources of crosstalk are vector quantities, so the magnitudes cannot be simply added together to obtain the total crosstalk. in fact, there are conditions where driving additional circuits in parallel in a given configuration can actually reduce the crosstalk. areas of crosstalk for a practical AD8116 circuit, it is required that it be mounted to some sort of circuit board in order to connect it to power supplies and measurement equipment. great care has been taken to create a characterization board (also available as an evaluation board) that adds minimum crosstalk to the intrinsic device. this, however, raises the issue that a system? crosstalk is a combination of the intrinsic crosstalk of the devices and the
AD8116 C14C rev. b circuit board to which they are mounted. it is important to try to separate these two areas of crosstalk when attempting to minimize its effect. in addition, crosstalk can occur among the input circuits to a crosspoint and among the output circuits. techniques will be discussed for diagnosing which part of a system is contributing to crosstalk. measuring crosstalk crosstalk is measured by applying a signal to one or more channels and measuring the relative strength of that signal on a desired selected channel. the measurement is usually expressed as db down from the magnitude of the test signal. the crosstalk is expressed by: | xt | = 20 log 10 ( asel ( s )/ atest ( s )) where s = j is the laplace transform variable, asel ( s ) is the amplitude of the crosstalk-induced signal in the selected chan- nel and atest ( s ) is the amplitude of the test signal. it can be seen that crosstalk is a function of frequency, but not a function of the magnitude of the test signal. in addition, the crosstalk signal will have a phase relative to the test signal associated with it. a network analyzer is most commonly used to measure crosstalk over a frequency range of interest. it can provide both magnitude and phase information about the crosstalk signal. as a crosspoint system or device grows larger, the number of theoretical crosstalk combinations and permutations can become extremely large. for example, in the case of the 16 16 matrix of the AD8116, we can examine the number of crosstalk terms that can be considered for a single channel, say in00 input. in00 is programmed to connect to one of the AD8116 outputs where the measurement can be made. first, we can measure the crosstalk terms associated with driv- ing a test signal into each of the other 15 inputs one at a time. we can then measure the crosstalk terms associated with driving a parallel test signal into all 15 other inputs taken two at a time in all possible combinations; and then three at a time, etc., until, finally, there is only one way to drive a test signal into all 15 other inputs. each of these cases is legitimately different from the others and might yield a unique value depending on the resolution of the measurement system, but it is hardly practical to measure all these terms and then to specify them. in addition, this describes the crosstalk matrix for just one input channel. a similar crosstalk matrix can be proposed for every other input. in addition, if the possible combinations and permutations for connecting inputs to the other (not used for measurement) outputs are taken into consideration, the numbers rather quickly grow to astronomical proportions. if a larger crosspoint array of multiple AD8116s is constructed, the numbers grow larger still. obviously, some subset of all these cases must be selected to be used as a guide for a practical measure of crosstalk. one common term is ?ll hostile?crosstalk. this term means that all other sys- tem channels are driven in parallel, and the crosstalk to the selected channel is measured. in general, this will yield the worst crosstalk number, but this is not always the case. other useful crosstalk measurements are those created by one nearest nei ghbor or by the two nearest neighbors on either side. these crosstalk measurements will generally be higher than those of more distant channels, so they can serve as a worst case measure for any other one-channel or two-channel crosstalk measurements. input and output crosstalk the flexible programming capability of the AD8116 can be used to diagnose whether crosstalk is occurring more on the input side or the output side. some examples are illustrative. a given input channel (in07 in the middle for this example) can be programmed to drive out07. the input to in07 is just terminated to ground and no signal is applied. all the other inputs are driven in parallel with the same test signal (practically provided by a distribution amplifier), but all other outputs except out07 are disabled. since grounded in07 is programmed to drive out07, there should be no signal present. any signal that is present can be attributed to the other 15 hostile input signals, because no other outputs are driven. thus, this method measures the all-hostile input contribution to crosstalk into in07. of course, the method can be used for other input channels and combinations of hostile inputs. for output crosstalk measurement, a single input channel is driven (in00 for example) and all outputs other than a given output (in07 in the middle) are programmed to connect to in00. out07 is programmed to connect to in15 which is terminated to ground. thus out07 should not have a signal present since it is listening to a quiet input. any signal mea- sured at the out07 can be attributed to the output crosstalk of the other 15 hostile outputs. again, this method can be modified to measure other channels and other crosspoint matrix combinations. effect of impedances on crosstalk the input side crosstalk can be influenced by the output imped- ance of the sources that drive the inputs. the lower the impedance of the drive source, the lower the magnitude of the crosstalk. the dominant crosstalk mechanism on the input side is capacitive coupling. the high impedance inputs do not have significant cur- rent flow to create magnetically induced crosstalk. from a circuit standpoint, the input crosstalk mechanism looks like a capacitor coupling to a resistive load. for low frequencies the magnitude of the crosstalk will be given by: | xt | = 20 log 10 [( r s c m ) s ] where r s is the source resistance, c m is the mutual capacitance between the test signal circuit and the selected circuit, and s is the laplace transform variable. from the equation it can be observed that this crosstalk mecha- nism has a high pass nature; it can be also minimized by reducing the coupling capacitance of the input circuits and lowering the output imped ance of the drivers. if the input is driven from a 75 ? terminated cable, the input crosstalk can be reduced by buffering this signal with a low output impedance buffer. on the output side, the crosstalk can be reduced by driving a lighter load. although the AD8116 is specified with excellent differential gain and phase when driving a standard 150 ? video load, the crosstalk will be higher than the minimum due to the high output currents. these currents will induce crosstalk via the mutual inductance of the output pins and bond wires of the AD8116.
AD8116 C15C rev. b from a circuit standpoint, this output crosstalk mechanism looks like a transformer with a mutual inductance between the windings that drives a load resistor. for low frequencies, the magnitude of the crosstalk is given by: | xt | = 20 log 10 ( mxy s / r l ) where mxy is the mutual inductance of output x to output y and r l is the load resistance on the measured output. this crosstalk mechanism can be minimized by keeping the mutual inductance low and increasing r l . the mutual inductance can be kept low by increasing the spacing of the conductors and minimizing their parallel length. one way to increase the load resistance is to buffer the outputs with a high input impedance buffer as shown in figure 27. the ad8079ar is a dual buffer that can be strapped for a gain of +2 (b grade = +2.2). this offsets the halving of the signal when driving a standard back-term inated video cable. the input of the buffer requires a path for bias current. this can be provided by a 500 ? to 5 k ? resistor to ground. this resistor also serves the purpose of biasing the outputs of the crosspoints at zero volts when all the outputs are disabled. in addition, the load resistor actually lowers the crosstalk com- pared to the conditions of the AD8116 outputs driving a high impedance (greater than 10 k ? ) or driving a video load (150 ? ). this is because the electric field crosstalk that dominates in the high impedance case has a phase of ?0 degrees, while the mag- netic field crosstalk that dominates in the video load case has a phase of +90 degrees. with a 500 ? to 5 k ? load, the contribu- tions from each of these is roughly equal, and there is some cancellation of crosstalk due to the phase differences. pcb layout extreme care must be exercised to minimize additional crosstalk generated by the system circuit board(s). the areas that must be carefully detailed are grounding, shielding, signal routing and supply bypassing. the packaging of the AD8116 is designed to help keep the crosstalk to a minimum. each input is separated from each other? input by an analog ground pin. all of these agnds should be directly connected to the ground plane of the circuit board. these ground pins provide shielding, low impedance return paths and physical separation for the inputs. all of these help to reduce crosstalk. each output is separated from its two neighboring outputs by analog supply pins of either polarity. each of these analog sup- ply pins provides power to the output stages of only the two adjacent outputs. these supply pins provide shielding, physical separation and low impedance supply for the channel outputs. individual bypassing of each of these supply pins with a 0.01 f chip capacitor directly to the ground plane minimizes high frequency output crosstalk via the mecha nism of sharing common impedances. each output also has an on-chip compensation capacitor that is individually tied to a package pin via the signals called agnd00 through agnd15. this technique reduces crosstalk by preventing the currents that flow in these paths from sharing a common impedance on the ic and in the package pins. these agndxx signals should all be connected directly to the ground plane. the input and output signals minimize crosstalk if they are located between ground planes on layers above and below, and separated by ground in between. vias should be located as close to the ic as possible to carry the inputs and outputs to the inner layer. the only place the input and output signals surface is at the input termination resistors and the output series back termi- nation resistors. these signals should also be separated, to the extent possible, as soon as they emerge from the ic package. +v s ad8079ar v s 1k 1k AD8116 outxx outyy AD8116 outzz outww 5v 0.1 f 75 75 75 75 0.1 f 10 f + +5v to other AD8116 outputs g = +2 g = +2 10 f + figure 9. buffering wired or outputs with the ad8079 evaluation board a four-layer evaluation board for the AD8116 is available. this board has been carefully laid out and tested to demonstrate the specified high speed performance of the device. figure 10 shows the schematic of the evaluation board. figure 11 shows the component side silk-screen. the layouts of the board? four layers are given in figures 12, 13, 14 and 15. the evaluation board package includes the following: fully populated board with bnc-type connectors. windows -based software for controlling the board from a pc via the printer port. custom cable to connect evaluation board to pc. disk containing gerber files of board layout. windows is a registered trademark of microsoft corporation.
AD8116 C16C rev. b 75 input 00 75 input 01 75 input 02 75 input 03 75 input 04 75 input 05 75 input 06 75 input 07 75 input 08 75 input 09 75 input 10 75 input 11 75 input 12 75 input 13 75 input 14 75 input 15 output 00 75 output 01 75 0.01 f av ee output 02 75 0.01 f av cc output 03 75 0.01 f av ee output 04 75 0.01f av cc output 05 75 0.01 f av ee output 06 75 0.01 f av cc output 07 75 0.01 f av ee output 08 75 0.01 f av cc output 09 75 0.01 f av ee output 10 75 0.01 f av cc output 11 75 0.01 f av ee output 12 75 0.01 f av cc output 13 75 0.01 f av ee output 14 75 0.01 f av cc output 15 75 0.01 f av ee 0.01 f av cc agnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 in00 agnd in01 agnd in02 agnd in03 agnd in04 agnd in05 agnd in06 agnd in07 agnd in08 agnd in09 agnd in10 agnd in11 agnd in12 agnd in13 agnd in14 agnd in15 data in clk data out 126 125 124 123 122 121 update reset ce nc nc nc nc nc nc 0.01 f 0.01 f 0.01 f dvcc dvee avee dgnd 0.01 f avcc 127 119 116 118 120 113 115 nc 105 112 nc 97 104, 128 agnd clip-on test points power supply connector * avcc00 out00 avee00/01 out01 avcc01/02 out02 avee02/03 out03 avcc03/04 out04 avee04/05 out05 avcc05/06 out06 avee06/07 out07 avcc07/08 out08 avee08/09 out09 avcc09/10 out10 avee10/11 out11 avcc11/12 out12 avee12/13 out13 avcc13/14 out14 avee14/15 out15 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 AD8116jst agnd 33 clip-on test points digital interface connector * dgnd data in update data out clk ce reset 0.01 f nc nc dvcc dvee avee av ee avcc av cc 0.01 f nc nc agnd av cc 0.01 f 56 63 49 55 46 48 43 45 42 34 39 36 35 40 38 37 41 agnd dgnd 0.1 f to pins 96,92,88,84 (avcc) to pins 94,90,86,82 (avee) 10 f 10 f 10 f 10 f * 6-pin 0.100 center header molex part nr. 22-23-2061 mating connector molex part nr. 22-01-03067 to pins 80,76,72,68 (avcc) to pins 78,74,70,66 (avee) 0.1 f 0.1 f 16 avcc 64 61 ++ + + nc = no connect 0.1 f figure 10. evaluation board schematic
AD8116 C17C rev. b figure 11. component side silkscreen
AD8116 C18C rev. b figure 12. board layout (top layer)
AD8116 C19C rev. b figure 13. board layout (signal layer)
AD8116 C20C rev. b figure 14. board layout (power layer)
AD8116 C21C rev. b figure 15. board layout (bottom layer)
AD8116 C22C rev. b optimized for video applications, all signal inputs and outputs are terminated with 75 ? resistors. figure 16 shows a cross- section of one of the input or output tracks along with the arrangement of the pcb layers. it should be noted that unused regions of the four layers are filled up with ground planes. as a result, the input and output traces, in addition to having con- trolled impedances, are well shielded. w = 0.008" (0.2mm) a = 0.008" (0.2mm) c = 0.028" (0.714mm) t = 0.00135" (0.0343mm) top layer signal layer power layer bottom layer b = 0.0132" (0.335mm) d = 0.0132" (0.335mm) figure 16. cross section of input and output traces the board has 32 bnc type connectors: 16 inputs and 16 outputs. the connectors are arranged in two crescents around the device. as can be seen from figure 13, this results in all sixteen input signal traces and all sixteen signal output traces having the same length. this is useful in tests such as all-hostile crosstalk where the phase relationship and delay between signals needs to be maintained from input to output. the four power supply pins avcc, dvcc, avee and dvee should be connected to good quality, low noise, 5 v supplies. where the same 5 v power supplies are used for analog and digital, separate cables should be run for the power supply to the evaluation board? analog and digital power supply pins. as can be seen in figure 17, there is extensive power supply decoupling on the evaluation board. figure 17 shows the location of all the decoupling capacitors relative to the ad81 16? pins. four large 10 f capacitors are located near the evaluation board? power supply connection terminals. these decouple the avcc, dvcc, avee and dvee supplies. because it is required that the voltage difference between dgnd and agnd never exceed 0.7 v, these grounds are connected by two antiparallel diodes. on the output side of the device (pin 65 to pin 96), the sixteen output pins are interleaved with the avcc and avee power supply pins. each of these pins is locally decoupled with a 0.01 f capacitor. these pins are also decoupled in groups of four with 0.1 f capacitors. due to space constraints the power supply pins 34 (dvcc) and 42 (dvee) are neither connected nor decoupled. these pins are, however, internally connected to dvcc and dvee (pins 127 and 119). as a general rule, each power supply pin (or group of adjacent power supply pins) should be locally decoupled with a 0.01 f capacitor. if there is a space constraint, it is more important to decouple analog power supply pins before digital power supply pins. a 0.1 f capacitor, located reasonably close to the pins, can be used to decouple a number of power supply pins. finally a 10 f capacitor should be used to decouple power supplies as they come on to the board.
AD8116 C23C rev. b 1 128 127 119 113 97 96 65 64 48 42 34 33 32 dvcc dvee avee 10 f10 f10 f *** * * * * * * * * * * 0.1 f 0.1 f * * * * * * * * * * 0.01 f * nc (dvcc) nc (dvee) nc = no connect 0.1 f 0.1 f 10 f avcc figure 17. detail of decoupling on evaluation board
AD8116 C24C rev. b controlling the evaluation board from a pc the evaluation board include windows-based control software and a custom cable that connects the board? digital interface to the printer port of the pc. the wiring of this cable is shown in figure 18. the software requires windows 3.1 or later to operate. to install the software, insert the disk labeled ?isk #1 of 2?in the pc and run the file called setup.exe. additional installation instructions will be given on-screen. before begin- ning installation, it is important to terminate any other windows applications that are running. reset clk data in dgnd ce update molex 0.100" center crimp terminal housing 1 6 d-sub 25 pin (male) 14 1 25 13 evaluation board pc 2 3 4 5 6 25 3 1 4 5 2 6 signal ce reset update data in clk dgnd molex terminal housing d-sub-25 figure 18. evaluation board-pc connection cable when you launch the crosspoint control software, you will be asked to select the printer port you are using. most modern pcs have only one printer port, usually called lpt1; however, some laptop computers use the prn port. figure 19 shows the main screen of the control software in its initial reset state (all outputs off). using the mouse, any input can be connected with one or more outputs by simply clicking on the appropriate radio buttons in the 16 16 on-screen array. each time a button is clicked on, the software automatically sends and latches the required 80-bit data stream to the evaluation board. an output can be turned off by clicking the appropriate button in the off column. to turn off all outputs, click on reset. the software offers volatile and nonvolatile storage of configu- rations. for volatile storage, up to two configurations can be stored and recalled using the memory 1 and memory 2 buffers. these function in an identical fashion to the memory on a pocket calculator. for nonvolatile storage of a configuration, the save setup and load setup functions can be used. this stores the configuration as a data file on disk. overshoot on pc printer ports?data lines the data lines on some printer ports have excessive overshoot. overshoot on the pin that is used as the serial clock (pin 6 on the d-sub-25 connector) can cause communication problems. this overshoot can be eliminated by connecting a capacitor from the clk line on the evaluation board to ground. a pad has been provided on the solder-side of the evaluation board to allow this capacitor to be soldered into place. depending upon the overshoot from the printer port, this capacitor may need to be as large as 0.01 f.
AD8116 C25C rev. b figure 19. screen display of control software
AD8116 C26C rev. b outline dimensions dimensions shown in millimeters and (inches). metric measurements are not rounded. english measurements are rounded. 128-lead plastic lqfp (st-128a) 0.006 (0.15) 0.002 (0.05) 0.030 (0.75) 0.024 (0.60) 0.018 (0.45) seating plane 0.063 (1.60) max standoff 0.003 (0.08) max top view (pins down) 1 32 33 65 64 96 97 128 0.551 (14.00) bsc 0.630 (16.00) bsc 0.488 (12.40) bsc 0.630 (16.00) bsc 0.488 (12.40) bsc 0.551 (14.00) bsc 0.009 (0.23) 0.005 (0.13) 0.016 (0.40) bsc 7 0 0.057 (1.45) 0.053 (1.35)
location page data sheet changed from rev. a to rev. b. correction to pin number in pin function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 revision history AD8116 C27C rev. b
c01071aC0C6/01(b) printed in u.s.a. C28C

▲Up To Search▲

Price & Availability of AD8116

	To Download AD8116 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .